This invention relates to improved methods of making semiconductor devices, and more particularly to a heat treatment step to be used in a method of making N-channel MOS integrated circuits which employs ion implant techniques.
MOS memory devices, particularly random access memories or RAM's, are being used for much of the storage in computers of all types. One of the most widely manufactured semiconductor devices at present is the N-channel, silicon-gate, MOS dynamic RAM, typically in 1K or 4K (1024 or 4096) bit size. These devices are described by Stein et al in IEEE Journal of Solid State Devices, Vol. SC-7, No. 5, Oct. 1972, and in U.S. Pat No. 3,909,631, issued Sept. 30, 1975 to N. Kitagawa, as well as in Electronics magazine, Sept. 13, 1973, p. 116-121.
One of the steps typically used in the manufacture of these devices is the formation of a shallow P+ type region over some of the surface of the silicon slice for the purpose of preventing unwanted or parasitic MOS devices from existing. This region is referred to as the channel stop. Ordinarily it is formed by a boron implant, i.e., by implanting boron atoms using an ion beam. The effect of implantation on the crystalline structure of silicon is described by Prussin and Fern in Journal of Electrochemical Society, Vol. 122, No. 6, June, 1975.
It has been determined that the damage to the crystalline structure and the impurity concentration profile resulting from the ion implant process have caused undesirable characteristics in memory devices. For example, the refresh time, or the time period between necessary refresh cycles in operation of the memory system, is a function of temperature. As temperature increases, the tendency for the charge stored in an oxide-dielectric MOS capacitor in conjunction with the depletion and inversion layers underneath, as used for storang cells in these devices, to leak off, also increases. The devices are advertised and sold with certain temperature specifications, i.e., they should be operable over the range from 0.degree. to 70.degree. C, ambient temperature, for example. The devices are often used in systems which have a clock cycle or machine cycle of about 400 ns; in this context, the time between refresh cycles should not be less than about 2 milliseconds. The system must be designed to read out all the data in memory and write it back in to "refresh" it at certain intervals, but this is unproductive overhead on the system and must be minimized. Once every several thousand machine cycles is acceptable, but the system is designed around a certain specified refresh time, and devices not meeting this specification at higher temperatures are not acceptable.
Another effect of the boron implant technique is that the unwanted capacitance between some elements of the semiconductor structure and the substrate is unduly high. This causes the maximum operating speed of the devices to be lower than desired. The capacitance of a reverse biased P-N junction is dependent upon the width of the depletion region, and for a given voltage across the junction the depletion region extends for a distance dependent upon impurity concentration and its profile. Lowering impurity concentration reduces capacitance, which is desirable in this case. The impurity profile resulting from the process of this invention has a favorable effect on parasitic capacitance and thus speed.
It is the primary object of this invention to provide an improved method of making semiconductor devices, particularly N-channel, silicon-gate MOS devices. Another object is to increase the "refresh time" characteristics of MOS memory devices at high temperatures. A further object is to reduce leakage associated with ion implantation in semiconductor devices which have been subjected to ion implant. Another object is to provide MOS memory devices which operate at higher speeds.